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+2 votes

asked in Digital Logic by Loyal (6.8k points) | 185 views

2 Answers

+5 votes
Best answer

My answer :- RS 60 :)

answered by Boss (42.6k points)
selected by
Using de' morgan's law, C' + B' can be replaced with (CB)'.
A'.(C.B)' + A.D'
3 NOT gates , 3 2-input AND gates, 1 2-input OR gate
= 3*5 + 3*10 + 10
= 55
This should be the minimum, right?
0 votes

Given F= AD'+A'C'+A'D'C'+A'B'C

From K-map, Minimized F will be F=A'B'+A'C'+AD'

Cost of each minterm

A'B'(2 input AND gate and 2 inverters)=10+5+5=20,

A'C'(2 input AND gate and 2 inverters)=10+5+5=20,

AD'(2 input AND gate and 1 inverter)=10+5=15,

F(3 input OR gate)=3*5=15

The total cost is 20+20+15+15=Rs 70

answered by Loyal (6.1k points)
the minimized would be ~A~B+~A~C+A~D giving 60....actually I read it incorrectly and thought minimum number of gates
Can you show how you got minimized ~A~B+~A~C+A~D?

Also, You have not considered the cost of OR gate here. 60+ cost of using 3 input OR gate =60+15=75 gives the total minimum cost realization of F
by using karnaugh should be 65(including the three OR)
Okay, now I have solved using K map and the answer comes to 70.
why are u taking ~A twice in calculating the cost..the first one will be used in the second input
Each term(not literal) is a minterm(2-input gate makes one minterm) and therefore we cannot take A' as common. It is SOP form. If we were to take A' as common, then what's the use of minimizing it with K-map?
by taking common I mean, use only one inverter, not two...and the  circuit you designed above gives the cost of 65...

I am still of the opinion that we cannot take only one inverter, since inverter is an input to the two different the AND gates A'C' and A'B'. Though, it is the same inverter that is used, but it is used twice with different combination of another input to the gate. In the question it is mentioned that all gates cost Rs.5 per input. You are just calculating the number of inverters and number of gates(AND/OR) but not checking from where the input is coming/going to.

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