Average number of memory accesses per instruction = $1+0.2+0.2=1.4$ (including for the instruction fetch)
We are having a unified L1 cache – so both instruction and data compete for the same cache. So, while calculating the stalls per instruction, instruction fetch also should be considered just like a data access.
Stalls per memory access $= \underbrace{0.016 \times 60}_{\text{cache miss}} + \underbrace{0.016 \times 0.15 \times 60}_{\text{dirty block}} = 0.96 + 0.144 = 1.104$ cycles
So, average stalls per instruction $ = 1.4 \times 1.104 = 1.5456$
So, effective CPI $ = 1.4 + 1.5456 = 2.9456.$