GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 30

Question

Consider a CPU with an average CPI of $1.4$ when all memory accesses hit on the cache.
Assume an instruction mix
$$\begin{array}{|c | c|}
\hline
\text{ALU }& 45\%\\
\text{LOAD} & 20\%\\
\text{STORE} & 20\%\\
\text{BRANCH} & 15\%\\
\hline
\end{array}$$
If the cache miss rate is $1.6\%$ and miss penalty is $60$ cycles, calculate the effective CPI for a unified $L1$ cache using write back and write allocate policy with the probability of a cache block being dirty being $0.15$ (round off to $2$ decimal places).

Answer 1

Average number of memory accesses per instruction = $1+0.2+0.2=1.4$ (including for the instruction fetch)

We are having a unified L1 cache – so both instruction and data compete for the same cache. So, while calculating the stalls per instruction, instruction fetch also should be considered just like a data access.
    
Stalls per memory access $= \underbrace{0.016 \times 60}_{\text{cache miss}} + \underbrace{0.016 \times 0.15 \times 60}_{\text{dirty block}} = 0.96 + 0.144 = 1.104$ cycles
    
So, average stalls per instruction $ = 1.4 \times 1.104 = 1.5456$
    
So, effective CPI $ = 1.4 + 1.5456 = 2.9456.$

Comments

@gatecse

Got it Sir !

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can you please explain this?

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Didn’t got the second step

average stall cycles =1.4*1.104

@Deepak Poonia sir please explain this question