Assuming that we can maintain the peak bandwidth, the memory system can support $(16 \times 10^9)/64 = 250$ million block references per second.
Since, a cache miss takes $64\;ns,$ in worst case (assume all accesses to be misses) we need to support $250 \times 10^6 \times 64 \times 10^{-9} = 16$ outstanding misses.