GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 16

Question

Which option is the correct order for transfer of a block of data?

1. The peripheral device (such as disk controller) will request the service of DMA by pulling DREQ high
2. CPU will finish the present bus cycle (not necessary the present instruction) and respond to the DMA by putting high on its HLDA.
3. DMA will put high on its HRQ, signalling the CPU through its HOLD pin that it needs to use the buses.
4. DMA will activate DACK which tells peripheral device that it will start to transfer the data.
5. DMA starts transferring from memory to peripheral by putting the address of first byte of block on the address bus and activating MEMR.
6. DMA decrements the counter and increment the address points and repeats until count zero.
7. When finished deactivate HRQ now it can regain control over its buses.

• A. $(a)(c)(b)(d)(e)(f)(g)$
• B. $(a)(b)(d)(e)(f)(c)(g)$
• C. $(a)(b)(c)(d)(e)(f)(g)$
• D. $(c)(b)(a)(d)(e)(f)(g)$

Comments

Any reference to study this??

Answer 1

The correct order would be option A.