CO: SpeedUp in Pipeline

Question

A non-pipeline processor has a clock rate 3 GHz and an average CPI of 4. An upgrade to the processor introduce 5 stage pipeline. How ever due to internal delay the clock rate of the new processor has to be reduces to 2 GHz. What is the speed-up of pipeline over non-pipeline?

• 3.1
• 3.3
• 3.5
• 3.8

I got 2.66 But the Given is 3.3 

Answer 1

Speed up = Time without pipeline / Time with pipeline

Time without pipeline= 4 clock cycle

1 clock cyle = 1 / (3 *10^9)

Time with pipeline = 1 clock cycle in ideal case

1 clock cycle= 1/ (2 * 10^9)

 

so, speed up= (4 * 1 / (3 *10^9)) / 1/ (2 * 10^9)

CORRECT ANS is 2.66

Answer 2

Twp=400/3

Tw=52

Spped up=Twp/Tp=2.56

Answer 3

let us assume number of instructions=100

execution time without pipeline=number of instructions*no.of clocks per instruction*delay

                                            =100*4*1/3*10^9=133.33 ns

execution time with pipeline=1(1st instruction)*number of stages*delay+(100-1)*1*delay

                                       =1*5*1/2*10^9+99*1/2*10^9=52 ns

speed up=T without pipeline/T with pipeline=

          =133.33/52=2.56

hence the given answer is wrong

Comments

we have to take CPI =1 for Pipeline it is ideal Case

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You can't assume number of instruction to be 100, you have to always comsider system in stable state.