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+26 votes

Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?

- $11, 00$
- $01, 10$
- $10, 01$
- $00, 11$

+14 votes

Best answer

For a cross-coupled $R-S$ flip flop with two NAND gates $11$ is no change and $00$ is forbidden. $00$ is forbidden (not allowed but not indeterminate) because in this state both $Q$ and $Q'$ equals $1.$ Moreover, in this state if inputs are changed to $11,$ next state is indeterminate (meaning we cannot determine the output)- $Q$ can be $0$ and $Q'$ can be $1$ or $Q = 1$ and $Q' = 0.$ There is also a chance that outputs can oscillate here when the following happens:

- Inputs are set to $11$
- When both inputs of NAND gates are $1$ output is $0$
- Suppose NAND gate 1 becomes $0$ first.
- This $0$ goes as input to NAND gate $2$.
- By this time NAND gate $2$ produces its own output as $0$.
- Now, this $0$ goes as input to NAND gate $1$ which makes its output $1$.
- The $0$ input to NAND gate $2$ (from step $4$) now makes its output $1.$
- Whole cycle can repeat and output toggles between $1$ and $0.$

This is just a possibility and that is why question says "may oscillate."

The input sequence 00,11 (Option D) may oscillate.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch

0

The answer should be 11,00 because in the question it is given the S-R is flip flop not a latch so there should be clock and whenver there is clock then in S-R flip flop same ouptput i.e. Q and Q' is same when both input is 11. So further proceed according to the given answer.

0

Agreed.** The question is ambiguous.** A flip-flop is a clocked latch. That being said, sometimes the 2 terms are used interchangeably^{1}. Since the RS "Flip flop" has been realized with only two NAND gates, the only way to do this is by assuming the question means "latch".

1: Reference: Latches and Flip Flops (EE 42/100 Lecture 24 from Berkeley) *"...Sometimes the terms flip-flop and latch are used interchangeably..."*

+21 votes

For R-S flip flop with NAND gates (inputs are active low) $11$-no change $00$-indeterminat. So, option **(A) **may make the system oscillate as "$00$" is the final input. In option **(D)**, after "$00$" flipflop output may oscillate but after "$11$", it will be stabilized.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch

+1

It is RS flip flop using NAND gates. So, 00 input causes indeterminate output.

@aravind90 00 cause indeterminate state which MAY lead to oscillation.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://www.iitg.ernet.in/asahu/cs221/Lects/Lec13.pdf

@aravind90 00 cause indeterminate state which MAY lead to oscillation.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://www.iitg.ernet.in/asahu/cs221/Lects/Lec13.pdf

0

An RS flip flop can be clocked or non clocked (also called latch). If it is non clocked, as in the question, it does not need a clock, then the 11 to 00 transition will cause indeterminate state, option A. Whereas in a flip flop which is clocked we have additional stage for clocking, which causes the 00 to 11 to oscillate.

0

@Arjun sir

question says flip flop(which is clocked) not latch(no clock). you have given references in which **latch table** is shown. NPTEL video clearly shows if it is R-S flip flop and uses NAND then 11 will cause indeterminate output and 00 memory. SO * D *must be the answer.

check it:

0

Right. They may be referring to SR latch. But this creates confusion . Saying flip flop and giving only 2 NAND gates are self contradictory.

0

@Arjun Sir

@Praveen Sir

plz tell me

but Sir how do we know for latch only 11 to 00 causes oscillation but not 00 to 11?

because there must be a difference in delay from S to R in case of 00 to 11 (or) 11 to 00

and why for flipflop the opposite case happens?

@Praveen Sir

plz tell me

but Sir how do we know for latch only 11 to 00 causes oscillation but not 00 to 11?

because there must be a difference in delay from S to R in case of 00 to 11 (or) 11 to 00

and why for flipflop the opposite case happens?

0

@srestha I considered flip-flop and latch the same for this answer as per Wikipedia.

Actually flip-flop refers to a clocked latch, that is output is produced only when the input clock is active.

Now the question here is not ambiguous. It clearly states R-S flip flop realized using 2 NAND gates which are cross-coupled. So, even if we consider it as clocked circuit, we are not using NAND gate there - it can be an AND gate. Suppose we use NAND gate for clocking, we NAND say S and the clock. So, when clock is active we get active output when S is 0, not when S is 1 (0 NAND 1 = 1). i.e., inputs are toggled here by the NAND gates. This is shown in the NPTEL video also.

+4

@Arjun Sir, there is no standard definition that says flip flop are clocked one's only. Wikipedia also says "Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered)"

And in this question, it is clear that we are talking about WITHOUT clock only, because they specifically mentioned that "using 2 NAND gates".

So they must be taliking about this only.

Now, If we try to implement clock using AND gates, this will not be possible.

This above diagram is not even a "flip-flop", it is something else, may be something useful/useless.

Flip flops have memory state at clock =0 (We make clock zero and then we leave flip flops as it is, Now in this state no change in input would reflect to output. When we need to store anything else, we make clock 1, give input accordingly then again make clock zero.)

This does not act as a memory when clock is zero. Because if clock is zero, then AND gates o/p are 0, and If one of the input of NAND is zero then it produces 1.

Now if we use AND gates with cross coupled NOR then it is flip flop.

Here if we make clock zero then AND gate o/p is zero, but nor gate output is not static. It acts as memory at clock zero.

So our final circuit is this only.

And this oscillates at 11, not at 00. therefore D must be answer.

Please comment if anything wrong :)

(Two things i did not find after searching-

1. No clear Standard distinction between latch and flip flop. though "commonly" flip-flops are clocked.

2. SR flip flop with AND-NAND combination )

here it is clearly mentioned that in this circuit if 11 comes after 00 then output may lead to oscillation and will eventually become either 0 or 1 (which also we don't know, its unpredictable, That's why we don't use SR flip flop if possible input is $11$. Slide 5 here is related to this.)

0

@Sachin Question asks for input sequence, not the values of S and R. In cross-coupled NAND case, inputs are active low.

https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch

0

@Sir, By default inputs are active high. If they ever want to use active low input, then they should specify explicitly.

+2

@Arjun Sir,

Can u please see this question

https://gateoverflow.in/1015/gate2004-18-isro2007-31

Here what should be answer ?

I think it should be C, but people are giving D as answer.

Intermidiate state is possible at 11, not at 00, right sir ?

Can u please see this question

https://gateoverflow.in/1015/gate2004-18-isro2007-31

Here what should be answer ?

I think it should be C, but people are giving D as answer.

Intermidiate state is possible at 11, not at 00, right sir ?

+1

An **SR latch** (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an **SR latch**.

0

@ VS is RS latch different from SR?

Please tell one thing S R (11) output is indeterminate

(00) output is no change

For RS are the 2 meanings flipped?

+7 votes

" a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation "

Oscillation means output is going to change every time.

As, 2 NAND gates are there , other 2 might be AND gate.

Now, circuit diagram will be like this

**A) **Now, at first R is getting 1 , that corresponding NAND gate producing 0.

That 0 is input of another NAND gate,

So, NAND gate corresponding to S getting input as 1 NAND 0=1 (As shown in picture below)

Now, it's **1st** output is** 0 1**

Next, 0 1 ouput is giving input to R and S

So, AND gate of R is producing 0 AND 1=0

NAND gate of R is giving 0 NAND 1=1(See picture again)

Similarly , AND gate of S getting input 1AND 1=1

R value previously was 0 (We donot know, R will produce first or S will produce first, So, taking previous value of R)

for NAND gate it is getting 0 NAND 1=1

So, **2nd **output here is **1 1**

Similarly keep check 1 1 as input as next AND gates

it will produce** 0 0**

So, if we put 11 as first input, it will keep toggleing , producing 01--11--00--11--00-------------------

**D)** if we give 00 first in same circuit it will produce as output 00--11--11--11--11------------------

So, output will not toggle ,after reaching 11 state.

**B)** if we give 01 as input it will produce 10--11--10--11----------------

means only S (or we can say any one output) will toggle , but not both.

**C)**Similar reason as B)

0

why did you use connection from Q to S , and Q' to R, this isnt the def of SR, its JK, ?!?

else the explanation seems right..

else the explanation seems right..

0

thank u.

see again , that connection not in JK.

that is the additional connection I have done due to this question perspective.

if any more doubt?

see again , that connection not in JK.

that is the additional connection I have done due to this question perspective.

if any more doubt?

0

question perspective?!? nothing is given else cross coupling, and if we consider that ones entered, the f/f wont recover from S-R 11 i guess

0

yes, seems right for initiating the clocking sequence.. i still need some practice on sequential circuits

0

I appreciate your efforts for making diagram but I have same question as Nitin raised, Why you connected Q to S ?

0

Thnks to u again :)

But I figured out that this is not even a flip flop.

Can you check my comment here? and then plz re comment if you find something wrong in that.

0

When both are 0 then if gate delay is also same then both anan will give output as 1.

Now this 1 will be feeded back to annd gates,and the other input is still 0 which will give 1 again.

Where is the oscilation?

Now this 1 will be feeded back to annd gates,and the other input is still 0 which will give 1 again.

Where is the oscilation?

+1

srestha pls see this,how this two are equivalent cross coupled nand gate.not getting this .

http://www.eng.auburn.edu/~strouce/class/elec4200/flip-flop.pdf

http://cse.yeditepe.edu.tr/~ayildiz/attachments/flipflops.pdf

0 votes

The answer Is surely D, but i will try to give the proper reason as far as i know about this concept.... SR flip flop with NAND gate has memory state at 11 and indetrminate state at 00.

Now what actually meant by INDETERMINATE STATE is that on application of 00 both Q and Q' both become 11. Well thats not a problem but problem is when we apply input combination 11. On application of input combination 11(which is a memory state) either Q becomes 1 and Q' becomes 0 or vice versa which in fact is actually INDETERMINATE, Because it depends on the delay of the 2 used NAND gates. That NAND gate which has minimum delay will lead its output to 1 and NAND gate with higher delay will lead its output to 0. So, this output combination is not fixed and will be different in different circuit. so, this way the input combination 00 is indeterminate.

Now if both NAND gates and the associated wires have the same delays, both outputs will oscillate indefinitely with a period of 2 gate delays.And Thats the case when RS Flip flop may oscillate.

So yes once again answer is D

Now what actually meant by INDETERMINATE STATE is that on application of 00 both Q and Q' both become 11. Well thats not a problem but problem is when we apply input combination 11. On application of input combination 11(which is a memory state) either Q becomes 1 and Q' becomes 0 or vice versa which in fact is actually INDETERMINATE, Because it depends on the delay of the 2 used NAND gates. That NAND gate which has minimum delay will lead its output to 1 and NAND gate with higher delay will lead its output to 0. So, this output combination is not fixed and will be different in different circuit. so, this way the input combination 00 is indeterminate.

Now if both NAND gates and the associated wires have the same delays, both outputs will oscillate indefinitely with a period of 2 gate delays.And Thats the case when RS Flip flop may oscillate.

So yes once again answer is D

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