GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 30

Question

We have a RISC processor with register-register arithmetic instructions that have the format $R_1\leftarrow R_2\; op\; R_3.$ The pipeline of these instructions runs with a $3$ GHz clock with the following stages: Instruction fetch $= 1$ clock, instruction decode $= 2$ clocks, fetch operands $= 1$ clock, execute $= 3$ clocks and store results $= 2$ clocks. What rate(in MIPS) can we execute register-register instructions that have no data dependencies with other instructions?

Comments

Remember this quote by me: Units play a very important role in life.😭

Answer 1

Given:
        $\begin{array}{|c c c c c|}
            \hline
            \textbf{IF} & \textbf{ID} & \textbf{FO} & \textbf{EX} & \textbf{Store} \\
            \hline
            1 & 2 & 1 & 3 & 2 \\
            \hline
        \end{array}$

    $1$ clock cycle $\rightarrow \dfrac{1}{3\times 10^9}$ seconds
    
    $\max (IF,ID,FO,EX,Store) = 3$ clock cycles
    
    $\dfrac{3}{3\times 10^9}$ seconds $\rightarrow 1$ instruction
    
    $1 \text{ second}\rightarrow   10^9$ Instructions
    
    So, rate in MIPS is $1000$ MIPS.

Comments

@gatecse Sir, how is 3 clock cycles implies 1 instruction? Aren’t 3 clock cycles stands only for one stage of an instruction?