GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 29

Question

Consider a $5$ stage MIPS Pipeline with the following features:

• For a non-pipeline implementation, ALU operations and branches take $3$ cycles while memory operations take $5$ cycles and clock rate is $3$ GHz
• Relative frequencies of ALU operations, branches and memory operations are $55\%, 15\%$ and $30\%.$
• In the pipeline due to clock skew and setup time, the clock cycle time increases by $0.65$ ns.

Calculate the estimated speedup (rounded to $2$ decimal points).

Answer 1

For non-pipelined processor :
    
Average instruction execution time $=\text{Clock cycle time} \times \text{Average CPI}$  

$\qquad =\dfrac{1}{3 \times 10^9}ns \times (0.55\times 3 + 0.15\times 3+0.30\times 5)=1.2\;ns$
    
For pipelined processor:
Clock cycle time $= 0.33 + 0.65 = 0.98\;ns$

Ideal speedup with pipelining (one instruction being completed in a cycle) $= \dfrac{1.2}{0.98}=1.224$

Comments

Why are we ignoring the effect of branch operations here? Branch operations contribute to stalls in the pipeline too...Also please explain how one instruction is completed in 1 clock cycle…

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@Deepak Poonia sir, @Sachin Mittal 1 sir please help understand why branch delays/stalls in the pipelined variant are not considered in this problem/solution

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@hmrishavbandy @looooommmm Sharing my opinion –

I believe that varies from implementation to implementation, eg. – whether a pipeline uses branch prediction or not, does it stall or execute another independent instruction while the effective address of the target instruction is getting compute, within how many phases it is doing so, etc. Without such details being mentioned, we compute the ideal speedup possible (when everything in the pipeline proceeds perfectly).