An instruction pipeline consists of following 5 stages:
IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back.
Now consider the following code:
1. LOAD R8, 0(R5); R8 = memory [R5]
2. LOAD R9, 4(R5); R9 = memory [R5 + 4]
3. ADD R7, R8, R9; R7 = R8 + R9
4. SUB R6, R7, R8; R6 = R7 – R8
Assume that each stage takes 1 clock cycle for all the instructions. How many cycles are required to execute the code, without operand forwarding over a bypass network?
- 9
- 10
- 11
- 14