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42 votes
42 votes

Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

  1. Transparent DMA and Polling interrupts
  2. Cycle-stealing and Vectored interrupts
  3. Block transfer and Vectored interrupts
  4. Block transfer and Polling interrupts

2 Answers

Best answer
50 votes
50 votes

CPU  get highest bandwidth in transparent DMA and polling. but it asked for I/O bandwidth not cpu bandwidth so option (A) is wrong.

In case of Cycle stealing, in each cycle time device send data then wait again after few CPU cycle it sends to memory . So option (B) is wrong.

In case of Polling CPU takes the initiative so I/O bandwidth can not be high so option (D) is wrong .

Consider Block transfer, in each single block device send data so bandwidth ( means the amount of data ) must be high . This makes option (C) correct.

edited by
24 votes
24 votes
The answer is option C .

In block transfer the entire block of data is transfered then only CPU again becomes the bus master

And in vectored Interrupts . I/o device along with interrupts send vector address of Interrupt Service routine which guides CPU to execute for a specific I/O device

Hence in both case BW will be required in a good amount !
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