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Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$, and $\text{Write Back } \textsf{(WB)}$. Each stage of the pipeline, except the $\textsf{EX}$ stage, takes one cycle. Assume that the $\textsf{ID}$ stage merely decodes the instruction and the register read is performed in the $\textsf{EX}$ stage. The $\textsf{EX}$ stage takes one cycle for $\textsf{ADD}$ instruction and the register read is performed in the $\textsf{EX}$ stage, The $\textsf{EX}$ stage takes one cycle for $\textsf{ADD}$ instruction and two cycles for $\textsf{MUL}$ instruction. Ignore pipeline register latencies.

Consider the following sequence of $8$ instructions:
$$\textsf{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL}$$ Assume that every $\textsf{MUL}$ instruction is data-dependent on the $\textsf{ADD}$ instruction just before it and every $\textsf{ADD}$ instruction (except the first $\textsf{ADD}$) is data-dependent on the $\textsf{MUL}$ instruction just before it. The $\textit{speedup}$ defined as follows.
$$\textit{Speedup} = \dfrac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forearding}}$$ The $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
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Best answer
33 votes
33 votes

Correct Answer: 1.875


$\text{Speedup(def in question)}=\cfrac{\text{Time without Operand Forwarding}}{\text{Time with Operand Forwarding}}$
Without Operand Forwarding:
$\tiny
\begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}\hline &1&2&3&4&5&6&7&8&9&10&11&12&13&14&15&16&17&18&19&20&21&22&23&24&25&26&27&28&29&30\\\hline \text{ADD}&\text{IF}&\text{ID}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{MUL}&&\text{IF}&\text{ID}&&&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{ADD}&&&\text{IF}&&&\text{ID}&&&&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{MUL}&&&&&&\text{IF}&&&&\text{ID}&&&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{ADD}&&&&&&&&&&\text{IF}&&&\text{ID}&&&&\text{EX}&\text{MEM}&\text{WB}\\\hline \text{MUL}&&&&&&&&&&&&&\text{IF}&&&&\text{ID}&&&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline \text{ADD}&&&&&&&&&&&&&&&&&\text{IF}&&&\text{ID}&&&&\text{EX}&\text{MEM}&\text{WB}\\\hline \text{MUL}&&&&&&&&&&&&&&&&&&&&\text{IF}&&&&\text{ID}&&&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline \end{array}$

$\text{Time taken without Operand Forwarding}=30$


With Operand Forwarding:
$\tiny \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}\hline &1&2&3&4&5&6&7&8&9&10&11&12&13&14&15&16\\\hline \text{ADD}&\text{IF}&\text{ID}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{MUL}&&\text{IF}&\text{ID}&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{ADD}&&&\text{IF}&\text{ID}&&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{MUL}&&&&\text{IF}&&\text{ID}&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{ADD}&&&&&&\text{IF}&\text{ID}&&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{MUL}&&&&&&&\text{IF}&&\text{ID}&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline
\text{ADD}&&&&&&&&&\text{IF}&\text{ID}&&\text{EX}&\text{MEM}&\text{WB}\\\hline \text{MUL}&&&&&&&&&&\text{IF}&&\text{ID}&\text{EX}&\text{EX}&\text{MEM}&\text{WB}\\\hline \end{array}$
$\text{Time taken with Operand Forwarding }= 16$


$\text{Speedup}=\cfrac{\text{Time without Operand Forwarding}}{\text{Time with Operand Forwarding}}=\cfrac{30}{16}=1.875$

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1 votes
1 votes

Speed Up = $\frac{23}{16} = 1.437 = 1.44$

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0 votes

without operand forwarding  when instruction j depends on instruction i then 

1st check the status of  WA state, if  WA state status is 1 then ID state read the data from WA state in next cycle so that we got time without operand forwarding technique =23

With operand forward technique :-

value of the data stored  EX state buffer then we can read it form there for  instruction form  so we get 16 cycles

speed up = 27/16

=1.68

 

Answer:

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