A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications:
\begin{array}{|l|c|c|c|} \hline \text {} & \textbf{Capacity }& \textbf{Mapping Method} & \textbf{Block Size}\\\hline \text{$I$-Cache} & \text{$4K$ words}& \text{Direct mapping} & \text{$4$ words} \\\hline \text{$D$-Cache} & \text{$4K$ words}& \text{$2$ -way set associative mapping} & \text{$4$ words}\\\hline \text{$L2$-Cache} & \text{$64K$ words}& \text{$4$-way set associative mapping} & \text{$16$ words} \\\hline \end{array}
The length of the physical address of a word in the main memory is $30$ bits. The capacity of the tag memory in the $I$-cache, $D$-cache and $L2$-cache is, respectively,
- $1$ K x $18$-bit, $1$ K x $19$-bit, $4$ K x $16$-bit
- $1$ K x $16$-bit, $1$ K x $19$-bit, $4$ K x $18$-bit
- $1$ K x $16$-bit, $512$ x $18$-bit, $1$ K x $16$-bit
- $1$ K x $18$-bit, $512$ x $18$-bit, $1$ K x $18$-bit