Is this question related to **computer science **as you are talking about **ADC??**

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For a dual slope ADC, the counter has a gated clock. The output voltage of integrator will rise upto T1 seconds with a positive slope of (-Va/RC). Va is assumed to be negative so that this slope is positive. Under this assumption, Vref is negative.

Now if Va increases, the slope increases. Therefore time to reach peak value T1 reduces. We know the counter starts counting from 0 until time T1. So if T1 reduces, the number of counts taken is also reduced. Therefore the number of counts is inversely proportional to Va. Hence option (D).

Now if Va increases, the slope increases. Therefore time to reach peak value T1 reduces. We know the counter starts counting from 0 until time T1. So if T1 reduces, the number of counts taken is also reduced. Therefore the number of counts is inversely proportional to Va. Hence option (D).

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