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refer this

http://cse10-iitkgp.virtual-labs.ac.in/cla_design.html

according to this for a 4 bit adder there has to be 2*4=8 gate levels. i.e. 2 per adder (AND and OR) and total 4 adders in a 4 bit adder.
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Ans should be $4$

$c_{i}=g_{i-1}+c_{i-1}.p_{i-1}$

$c_{1}=g_{0}+c_{0}.p_{0}$

$c_{2}=g_{1}+c_{1}.p_{1}$

$\Rightarrow c_{2}=g_{1}+\left ( g_{0}+c_{0}.p_{0}\right )p_{1}$

$\Rightarrow c_{2}=g_{1}+g_{0}.p_{1}+c_{0}.p_{0} .p_{1}$

$c_{3}=g_{2}+c_{2}.p_{2}$

$\Rightarrow c_{3}=g_{2}+\left (g_{1}+g_{0}.p_{1}+c_{0}.p_{0} .p_{1}\right )p_{2}$

$\Rightarrow c_{3}=g_{2}+g_{1}.p_{2}+g_{0}.p_{1}.p_{2}+c_{0}.p_{0} .p_{1}.p_{2}$

$c_{4}=g_{3}+c_{3}.p_{3}$

$\Rightarrow c_{4}=g_{3}+\left (g_{2}+g_{1}.p_{2}+g_{0}.p_{1}.p_{2}+c_{0}.p_{0} .p_{1}.p_{2}\right )p_{3}$

$\Rightarrow c_{4}=g_{3}+g_{2}.p_{3}+g_{1}.p_{3}+g_{0}.p_{1}.p_{2}.p_{3}+c_{0}.p_{0} .p_{1}.p_{2}p_{3}$

 

Note, for basic gate implementation $g_{0}=A_{0}.B_{0}$

$p_{0}=A_{0}\oplus B_{0}=AB'+BA'$

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