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All the logic gates in the circuit shown below have finite propagation delay. The circuit can be used as a clock generator, if

a) X = 0

b) X = 1

c) X = 0 or 1

d) X = Y

edited | 1.1k views

it looks like asynchronous sequential circuit.
here, Next state, $Y = x \oplus y$ , where $x$ is input , $y$ is present state

 Present state $y$ input $x$ Next state $Y$ 0 0 0 0 1 1 1 0 1 1 1 0

At $x=0$, circuit reach to stable state, if y is $0$, it will remain $0$, or if it is $1$ it will remain $1$.

At $x=1$ , states goes $0$ to $1$ , $1$ to $0$, so on , will not reach to stable state.

At $x=y$, next state will remain always at $0$, as seen in table.

so , At $x=1$ , the above circuit will generate the sequence of 0,1,0,1.. , can be used as clock generator.

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Means to use any circuit as clock generator, we should generate a sequence of $0,1,0,1,0,1.....$, means high voltage and low voltage.
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Sir  why  X=0  is not ryt plz explain
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At x=0, circuit reach to stable state, if y is 0, it will remain 0, or if it is 1 it will remain 1.

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nice explanation
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great
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"The circuit can be used as a clock generator", what is the meaning of this line??

what is the meaning of stable state in given solution??

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@Hira Thakur A clock signal is fluctuating - that's why we need something unstable.

We know for $\mathrm{XOR}$ gate that
$\mathrm{A \bigoplus B=A\bar{B}+\bar{A}B}$

So $1 \bigoplus \mathrm{A} =1\cdot\bar{\mathrm{A}}+\bar{1}\cdot\mathrm{A}=\bar{\mathrm{A}}+0\cdot\mathrm{A}=\bar{\mathrm{A}}$

It means any one input of $\mathrm{XOR}$ gate is $1$, the output will be the negation of the other input i.e. this $\mathrm{XOR}$ gate logically converts to $\mathrm{NOT}$ gate.

Here in the diagram the output $\mathrm{Y}$ of the $\mathrm{XOR}$ gate is fed into its own $\mathrm{XOR}$ gate. So if this gate can logically be converted into $\mathrm{NOT}$ gate, it will produce $0,1,0,1,...$ assuming initial state of $\mathrm{Y}$ as $0$.

That's why $\mathrm{X}$ should be $1$.

So the correct answer is b).

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