A) They have given operand forwarding should happen from EX stage to ID stage. Which means ID stage of I2 should happen after the EX stage of I1, which means
Now can we make 6 th clock-cycle as a split cycle ???
(Which means can we make both EX of I2 and ID of I3 in the 6 th clock-cycle (by doing EX in first half of clock-cycle and ID in 2nd half of clock-cycle) ??? )
To answer this, you need to first think what is meant by EX stage and what is meant by ID stage...?
EX stage means computing value using ALU unit and ID stage means Decoding the instruction and read the source registers from register file. Now we can definitely make EX stage in the first half of 6 th clock-cycle and ID stage in the 2 nd half of 6-th clock-cycle because one instruction is computing other is reading. (we always do split phase if 1 instruction is writing/computing and other instruction is reading but we will never do split phase if one instruction is computing and other instruction is also computing because ALU for 2 instructions cannot be done in a single clock-cycle. Example: EXECUTE-EXECUTE. Also we don't do split phase if one of the instructions is doing memory phase..the reason is generally memory phase alone needs atleast one clock-cycle).
Now coming back to your question, "Why I3 goes in ID stage in 6th cycle and not in 4th cycle ?"
Because EX means computing and ID means reading so we can definitely make both in the same clock-cycle.
B) Number of stall-cycles means number of clock-cycles where you are supposed to do some stage (fetch or decode or ..anything) but you are not doing because of
1) hardware needed for 1 stage is used by someother stage (structural hazard),
2) there is a data dependency (RAW hazard, WAR hazard , WAW hazard),
3) there is a control hazard (caused by BRANCH or JUMP instructions).
Now coming back to your question "number of stall-cycles here"
Here number of clock-cycles, where we are supposed to do some stage work but not doing any work because of hazards = 6
For 3rd instruction - c4 and c5 are 2 stall cycles For 4 th instruction - c4 and c5 are 2 stall cycles
For 5th instruction - c8 and c9 are 2 stall cycle . So totally 2+2+2 = 6 stall-cycles.