edited by
17,176 views
45 votes
45 votes

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement $X = (S - R * (P + Q))/T$ is given below. The values of variables $P, Q, R, S$ and $T$ are available in the registers $R0, R1, R2, R3$ and $R4$ respectively, before the execution of the instruction sequence.

$$\begin{array}{lll}  \text{ADD} & \text{$R5,R0,R1$} & \text{$;R5$} \leftarrow \text{R0 + R1} \\
\text{MUL}& \text{$R6,R2,R5$} & \text{$;R6$} \leftarrow \text{R2 * R5} \\
 \text{SUB} &  \text{$R5,R3,R6$} & \text{$;R5$} \leftarrow \text{R3 -R6}  \\ 
\text{DIV} &\text{$R6,R5,R4$} & \text{$;R6$} \leftarrow \text{R5/R4} \\
\text{STORE} &\text{$R6,X$}& \text{$;X$} \leftarrow \text{R6}  \\
\end{array}$$

The IF, ID and WB stages take 1 clock cycle each. The EX stage takes $1$ clock cycle each for the ADD, SUB and STORE operations, and $3$ clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

  1. $10$
  2. $12$
  3. $14$
  4. $16$
edited by

5 Answers

Best answer
81 votes
81 votes

$$\small \displaystyle \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline &C_1&C_2&C_3&C_4&C_5&C_6&C_7&C_8&C_9&C_{10}&C_{11}&C_{12}\\\hline
\textbf{ADD}&\text{IF}&\text{ID}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&&&&&\\\hline
\textbf{MUL}&&\text{IF}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{EX}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&&\\\hline
\textbf{SUB}&&&\text{IF}&\color{red}{-}&\color{red}{-}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&&&&\\\hline
\textbf{DIV}&&&&&&\text{IF}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{EX}&{\color{green}{\underset{\boxed{1}}{\text{EX}}}}&\text{WB}&\\\hline
\textbf{STORE}&&&&&& &\text{IF}&\color{red}{-}&\color{red}{-}&{\color{green}{\underset{\boxed{1}}{\text{ID}}}}&\text{EX}&\text{WB}\\\hline \end{array} $$

$\color{red}{-}\quad\text{Stalls}$
$\color{green}{\boxed{1}} \quad \text{Operand forwarding from EX-ID using split phase}$

So, answer is 12.

Correct Answer: $B$

Reference

edited by
26 votes
26 votes

answer = option D = $16$ cycles are required

5 votes
5 votes

Hi  , I have a very silly doubt here. 

Can we do the IF stage as I did ? because in other answers I could see , IF is also done after EX

amarVashishth 

srestha goel 

I have the confusion here that , IF stage of I4 instruction , can I start it in clock 4 ? because anyhow , ID should be started at  clock 7. or does IF also needs to start at clock 6 ?

Please clarify this doubt.

(N.B : please bear with my poor , illegible hand-writing )

edited by
Answer:

Related questions

42 votes
42 votes
2 answers
3
Ishrat Jahan asked Oct 31, 2014
11,732 views
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...