Consider 1 Ghz clock frequency processor , uses different operand accessing models shown below

Question

My question is : in the last indexed instruction , will it not be this way :

1 Memory Access + 1 Arithmetic computation + 1 Memory access = 2 + 3 + 2 = 7 clock cycles ?

Answer 1

for operand fetching (i.e. instruction is present in IR) in indexed mode Effective address= [BaseRegister]+ [Index Register]

and then data =[Effective Address]

therefore 1 reg reference + 1 arithmetic operation + 1 Memory reference i.e. 1+3+2

Comments

but what is the overall operand fetch rate rate shouldnt it be 2.7

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For immediate we take 0 or 1