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NPTEL Assignment Question
rsansiya111
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Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.
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Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.
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Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions are not found ... access time (including hit detection) is 1 clock cycle. The average access time of the memory hierarchy will be . nanoseconds
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