I have 3 doubts in the following solution:
Doubt 1: In red colour
While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem?
Doubt 2: In blue colour
We know that in the instruction decode stage of any instruction, register fetch also happens, so for I4, R2 and R7 register are to be fetched during Instr Decode stage of I4. Also, I1 WB stage is already accessing the register in cycle 5, so how can Decode stage of I4 happen in the same cycle?
Doubt 3: In green colour
Instructions I2,I3,I4 and I5 operate with register only so the memory-access stage shouldn't happen for these instructions, correct?
Solution as per my understanding: