GATE appliedroots test series

Question

I have 3 doubts in the following solution:

Doubt 1: In red colour
While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem?

Doubt 2: In blue colour
We know that in the instruction decode stage of any instruction, register fetch also happens, so for I4, R2 and R7 register are to be fetched during Instr Decode stage of I4. Also, I1 WB stage is already accessing the register in cycle 5, so how can Decode stage of I4 happen in the same cycle? 

Doubt 3: In green colour
Instructions I2,I3,I4 and I5 operate with register only so the memory-access stage shouldn't happen for these instructions, correct?

Solution as per my understanding:

Comments

Doubt 1: In red color

No, there is no structural dependency. A structural dependency exists when both I1 and I2 access memory areas at the same time.

Here I1 access memory area and I2 access IF area Both are different areas of memory.

 

Doubt 2: In blue color

In I4, there is no RAW dependency exist so there is no problem with that. As dependency exit than in RISC pipeline, WB stage work on two half cycle. In the first half cycle, the write-back procedure is done and in the other half cycle, register read.

 

Doubt 3: In green color

No, explain above.

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Thank you for answering.

Doubt 1 and 3 got resolved.

Doubt 2: I understand that there is no RAW dependency but the doubt is that both I1 and I4 are accessing registers in the same cycle. I know that they are writing/reading to/from different registers but they would be required to access the local bus at the same time and this cannot happen, hence the doubt.

Please provide me some links where I can read more about the half-cycle idea.

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Suppose in your home there is only one vehicle and two-person access the same vehicle at the same time then there is a conflict.

But If there are two vehicles then there is no conflict. Both can use at the same time

Same Here

Here in I1, R4 is written and in I4, R2 and R7 are read. So there is no conflict.

:)

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@Ashutosh_Mishra 

Please provide me some links where I can read more about the half-cycle idea.

Refer Carl Hamacher book for Computer Organization. 

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thank you, the half-cycle idea cleared the doubt.

For others having the same doubt, https://passlab.github.io/CSE564/notes/lecture05_Pipelining.pdf page 15-18 mention this concept.

Answer 1

doubt 1: there will be no structural dependency because there are two types of memory generally
→ instruction memory used in IF
→ data memory used in MEM, p.s. these two are entirely separate stages

doubt 2: already stated above (in somebody else’s answer) thank you for that

doubt 3: the MEM is  acting as a no-op stage for register specific instructions.