Computer System Architecture By M Morris Mano

Question

The floating-point pipeline are implemented
with combinational circuits.Suppose that the time delays of the four segments are t1=60ns, t2=70ns, t3=100ns, t4=80ns, and the interface registers have a delay of tr=10ns.

Solution: Pipeline floating-point arithmetic delay: tp=t3+tr=110ns
 Non-pipeline floating-point arithmetic delay:
tn=t1+t2+t3+t4+tr=320ns
 Speedup: 320/110=2.9

My Doubt: why register delay is added in non pipeline system?

Answer 1

Why register delay is added in non pipeline system?
After last stage, the result is being sent to the destination register.
Hence register delay for setting up bits in destination register must be considered.
For example consider a RISCV instruction
add t0, t1, t2
Suppose the execution of this instruction involves processing of this instruction through 5 stages.
After last stage the result will be sent to register t0,
So its delay must be considered, while calculating the total instruction processing time.