The floating-point pipeline are implemented
with combinational circuits.Suppose that the time delays of the four segments are t1=60ns, t2=70ns, t3=100ns, t4=80ns, and the interface registers have a delay of tr=10ns.
Solution: Pipeline floating-point arithmetic delay: tp=t3+tr=110ns
Non-pipeline floating-point arithmetic delay:
tn=t1+t2+t3+t4+tr=320ns
Speedup: 320/110=2.9
My Doubt: why register delay is added in non pipeline system?