In pipelined processor only $1^{st}$ instruction takes $k\times T_P$ time,

all other $(n-1)$ instructions take $1$ cycle time $=(n-1)\ T_P$

Total execution time on pipelined processor assuming no stalls $T_{EP}=k\space T_P+(n-1)T_P=(n-1+k)T_P$

Execution time of each instruction on non-pipelined processor $T_n= k\times T_P$

Total execution time on non-pipelined processor $T_E=n\space k\space T_P$

$Speed Up = \frac {\text{total execution time without pipeline}}{\text{total execution time with pipeline}}=\frac {T_E} {T_{EP}}=\frac{(n\space k\space )T_P}{(n-1+k)T_P}\approx k$

Approximation based on $n>>k,\therefore (n-1+k)\approx n$

Now, let $I$ is stalls per instruction in pipelined processor that is $I \times T_P$ time extra per instruction,