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Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words.Where in the cache (Set number in decimal)  is the word from memory location ABCDE888 mapped?

Let’s see what is given to us :

32 bit architecture

Cache size = 16 KB = $2^{14}$ B

set associativity = 4

It is given that line size is of four 32 bit words so we have to consider it as word addressable.

Block offset = log2(4) = 2bits

Line size = 4*32bits = 128bits = 16B

#cache lines = $\frac{cache size}{line size} =$ $\frac{2^{14}}{2^{4}}$ = $2^{10}$

#sets = $\frac{no. of lines}{set associativity}$ =  $\frac{2^{10}}{4}$ = $2^8$

 Tag (32-(8+2) = 22 bits) Set no. (8bits) Block offset (2bits)

Now given address is (ABCDE888) → 1010 1011 1100 1101 1110 1000 1000 1000 in binary

Set number bits are 00100010 and its decimal equivalent is 34.

by

yes i asked the team about this and they said if nothing is mentioned about the addressability of the main memory , then we need to assume it to be by default byte addressable hence the offset will be 4 bits i.e 16B per block.

But as you mentioned , all we need to do is keep the concepts strong.

edited by
Byte addressable is default if nothing is mentioned but here it is mentioned the cache size in words so I assumed it as word addressable . In GATE exam they will clearly mention if the memory is word addressable. You can also see in PYQ there is nearly 0 scope of ambiguity.

Absolutely right

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