in CO and Architecture edited by
237 views
0 votes
0 votes

Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.

in CO and Architecture edited by
237 views

2 Comments

yes, you are correct but can you tell me if there other special cases where a stall may happen such as in LOAD because it's a special case where you get results very late which causes a stall.
0
0

@Sagar475 stalls may happen in hazards like load use, structural, control etc.

control hazard is when a branch is taken and hence instructions currently in IF and ID stage are replaced with nop, in other words stalled.

structural hazard takes place when multiple pipeline stages simultaneously access memory or the same port of register file or any resource where there is exclusive access.

0
0

1 Answer

2 votes
2 votes
Answer is 12.

There are 2 load hazards which stalls the pipeline for 1 cycle each. There are 6 instructions hence total number of clock cycles to finish = 6 + 5 – 1 = 10.

Load hazards are

instruction pair (2, 3) and (4, 5)

Adding 2 stalls cycles we get 10 + 2 = 12.

Related questions