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Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop:

for (i = 1; i < = 1000; i++)
{I1, I2, I3, I4} 

where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ are given below:

$$\begin{array}{|c|c|c|c|c|} \hline & \textbf {S _1} &\textbf {S _2} & \textbf {S _3} & \textbf{S _4 } \\\hline \textbf{I1}& \text{1} & \text{2} & \text{1} & \text{2} \\\hline \textbf{I2} & \text{2} & \text{1} & \text{2} & \text{1}\\\hline \textbf{I3}& \text{1} & \text{1} & \text{2} & \text{1} \\\hline \textbf{I4} & \text{2} & \text{1} & \text{2} & \text{1} \\\hline \end{array}$$

The output of  $I1$ for $i = 2$ will be available after

1. $\text{11 ns}$
2. $\text{12 ns}$
3. $\text{13 ns}$
4. $\text{28 ns}$

@arjun sir , I think this options and answer selected is also wrong
Can u pls cross check it ? Im getting 23

Explanation given HERE seems to be more accurate .

That is a different question rt?
Sorry. My mistake !

Here it is asked output of I1 .
But Everywhere this GATE Question is asked count the total number of clock cycles !

Actual GATE Question is different . I was confused
No, see the table of stage delays.
Sorry sir, my mistake .  The Gate question I read was showing different stage delays and was also asking total number of cycles needed
sir i have a question as in above question it is using for loop so initialisations , condtion check, exection ,incement ok .. so if we executing I=2 then i1 for the second time then we can  done this after complete execution of I4 then only it can increment it again bcoz sir if it so then for 1000(termination ) instruction starting work would be wasted

Wrt the question and the selected answer given here, why aren't we considering all the above 4 pipeline stages to be of the same duration, i.e., the duration having the maximum length of 2 ns ??

Is it because in that question, constant clocking rate has been asked to be considered ?

edited
@the_bob

If your doubt is cleared then please let me know the reason too. What I believe is if there are synchronous transfer / constant clocking rate terms are used then we need to use max(d1, d2, d3) where d1, d2, and d3 is the delay of stages S1, S2, S3 because then we need to have constant transfer for all the stages. And if those above-mentioned terms aren’t used then consider time for each stage of instruction, then using summation and the required formula we can easily calculate as we have done in this problem. If I am wrong then please correct me.

$$\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {t1} & \textbf {t2} & \textbf {t3} & \textbf {t4} & \textbf {t5} & \textbf {t6} & \textbf {t7} & \textbf {t8} & \textbf {t9} & \textbf {t10} & \textbf {t11} & \textbf {t12} & \textbf {t13} \\\hline \textbf{I1}& \text{s _1} & \text{s _2} & \text{s _2} & \text{s _3} & \text{s _4} & \text{s _4} \\\hline \textbf{I2} & & \text{s _1} & \text{ s _1} & \text{ s _2} & \text{s _3} & \text{s _3} & \text{s _4}\\\hline \textbf{I3}& & & &\text{s_1} & \text{s_2} & \text{--}&\text{s_3} & \text{s _3} & \text{s _4}\\\hline \textbf{I4} & &&&&\text{s_1} & \text{s_1} & \text{s_2} & \text{--} & \text{s_3} & \text{s _3}& \text{s _4}\\\hline \textbf{I5} & &&&&&&\text{s_1} & \text{--} & \text{s_2} & \text{s _2} & \text{s_3} & \text{s _4}& \text{s _4}\\\hline \end{array}$$

So, total time would be $13\;ns$

Option (c).
by

I have the same doubt. Did you get an answer @Rishabh Gupta 2 ? Slowest stage time for each stage is considered in this question: https://gateoverflow.in/1063/gate2004-69. So why are we not doing the same here? Arjun sir also mentioned in a comment for that answer that if no information about clock rate is given, we must assume uniform clock rate. Therefore, clock period for this question should be considered as 2ns. Please correct me if I am wrong

There’s mistake here although this is giving the correct ans but for I5 s2 shd be in t8 and t9 and not in t9 and t10. correct me if i am wrong

ans) 13

### 1 comment

why have you done I1 I2 I3 I4 and again I1 for each stage.

Silly mistake should be taken care of

Remember we have to find second iteration of Instruction I1 finish time.

by

### 1 comment

Actually you made a silly mistake here. Check the answers given by others, there will be a stall at 8th clock cycle when I1 is executing for second time.