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Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops:

while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below:

  S1 S2 S3 S4 S5
I1 1 1 2 1 1
I2 1 2 1 1 1
I3 1 2 2 1 1
I4 2 1 2 1 1

Output of I4 will be available at _____.

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  S1 S2 S3 S4 S5
I1 1 2 4 5 6
I2 2 4 5 6 7
I3 3 6 8 9 10
I4 5 7 10 11 12
I1 6 8 12 13 14
I2 7 10 13 14 15
I3 8 12 15 16 17
I4 10 13 17 18 19

 

Hence, the output of I4 will be available at 19ns.

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Hi divyanshu

I've solved this question as like below image(2) because of buffer stored.

But when I searched more about this question I found that answer comes to be 19 and this make me conceptually weaker.

All problem comes into the picture because in the above image, 2nd I2 should come at 11 because until I3 of S1 will not start, till then I2 of S2 should not start and hence the answer should be 20

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