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Consider the following sequence of instructions

Add #20,R0,R1

Mul #3,R2,R3

And #\$3A,R2,R4

Add R0, R2, R5 

In all instructions, the destination operand is given last. Initially, registers R0 and R2 contain 2000 and 50, respectively. These instructions are executed in a computer that has a four-stage pipeline(Fetch, Decode, Execute and Write Back).  Assume that the first instruction is fetched in clock cycle 1, and that instruction fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____

There is no WAW, RAW and WAR dependency in given sequence of instructions , hence there will be no stall due to data hazard .

So number of cycles required = number of stages (k) + number of instructions (n) -1

= 4 + 4-1

= 7
by

1
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