Consider the following sequence of instructions
Add #20,R0,R1
Mul #3,R2,R3
And #$3A,R2,R4
Add R0, R2, R5
In all instructions, the destination operand is given last. Initially, registers R0 and R2 contain 2000 and 50, respectively. These instructions are executed in a computer that has a four-stage pipeline(Fetch, Decode, Execute and Write Back). Assume that the first instruction is fetched in clock cycle 1, and that instruction fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____