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A CPU has only three instructions $I1, I2$ and $I3,$ which use the following signals in time steps $T1-T5$:

$I1 : T1$ : Ain, Bout, Cin
$T2$ : PCout, Bin
$T3$ : Zout, Ain
$T4$ : Bin, Cout
$T5$ : End

$I2 : T1$ : Cin, Bout, Din
$T2$ : Aout, Bin
$T3$ : Zout, Ain
$T4$ : Bin, Cout
$T5$ : End

$I3 : T1$ : Din, Aout
$T2$ : Ain, Bout
$T3$ : Zout, Ain
$T4$ : Dout, Ain
$T5$ : End

Which of the following logic functions will generate the hardwired control for the signal Ain ?

1. $T1.I1 + T2.I3 + T4.I3 + T3$
2. $(T1 + T2 + T3).I3 + T1.I1$
3. $(T1 + T2 ).I1 + (T2 + T4).I3 + T3$
4. $(T1 + T2 ).I2 + (T1 + T3).I1 + T3$

Best Explained, thank you!
nice 1 kushagra

We just have to see which all options give $1$ whenever $A_{in}$ is $1$ and $0$ otherwise.

So, Ain is $1$ in $T3$ of $I1, I2$ and $I3$. Also during $T1$ of $I1$, and $T2$ and $T4$ of $I3$. So, answer will be

$T1.I1 + T2.I3 + T4.I3 + T3.I1 + T3.I2 + T3.I3$

Since CPU is having only $3$ instructions, $T3.I1 + T3.I2 + T3.I3$ can be replaced with $T3$ (we don't need to see which instruction and $A_{in}$ will be activated in time step $3$ of all the instructions).

So, $T1.I1 + T2.I3 + T4.I3 + T3$

by

edited by
T1
For anyone wondering about the concepts behind this, see page 426 of Hamacher 5th edition. They describe the generation of signal Zin, where it is said to be "asserted during time slot T1 for all instructions", so just T1 is written in the logic function. It's probably due to the way the logic circuit is designed (instruction decoder does not need to choose between instructions in time slot T1, the signal is active for all).
@pritishc do you have soft copy of the book??