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The storage area of a disk has the innermost diameter of $10$ cm and outermost diameter of $20$ cm. The maximum storage density of the disk is $1400$ bits/cm. The disk rotates at a speed of $4200$ RPM. The main memory of a computer has $64$-bit word length and $1$µs cycle time. If cycle stealing is used for data transfer from the disk, the percentage of memory cycles stolen for transferring one word is

  1. $0.5 \%$
  2. $1 \%$
  3. $5\%$
  4. $10\%$
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4 Comments

edited by
In cycle stealing mode how much time CPU is blocked. This is what is asked.

Max density will be provided by the innermost track & the diameter of the innermost track is given as 10 cm

So let's calculate track capacity:

$\\ Track\ capacity=circumference\times density=\dfrac{22}{7}\times 10cm\times\dfrac{1400\ bits}{cm}=5500B$

$\\ \dfrac{1}{70}sec\rightarrow5500B\\ \\ 1sec\rightarrow 385000B\\ ?\leftarrow 64bit\\ ?=20.77\mu s$

$x$=$20.77\mu s$ is data transfer time
$y$=$1\mu s$ is transfer time

% of time CPU blocked=$\dfrac{y}{x}=\dfrac{1}{20.77}\times 100=4.81\%$ $\approx 5\%$
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@KUSHAGRA गुप्ता @Kabir5454 @Abrajyoti00 @ankitgupta.1729

$\frac{1}{70} sec = 5500B$

$1 sec = 5500 * 70 = 385000$ (above 38500???)

Where I am wrong.

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The above comment there is one '0' missing as you mentioned. But the rest of the calculation of the above comment still correct.

385000 B ---------->1 sec

1 B.            ------------>$\frac{1}{385000}$ sec

64 bit (8 byte) -----------> $\frac{8}{385000}$ sec =0.00002077 sec = 20.77 $ \mu$s

Rest of the calculation is correct.

( I have edited the above comment as well)
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6 Answers

24 votes
24 votes
Best answer

In a disk all tracks have equal capacity and so data density is highest for the innermost track as it has the smallest radius. 

  • Maximum storage density (hence of innermost track) $=1400$ bits per cm 
  • Track capacity $\pi \times d \times 1400$ bits $ = 3.14 \times 10 \times 1400 = 43960$ bits

With $4200$ rotations per minute, data transfer rate $=\dfrac{4200 \times 43960}{60}$ bits per second.

Therefore, to transfer $64$ bits  time required $ = \dfrac{60}{4200 \times 43960}\times 64 = 20.798\mu s$

With $1\mu s$ memory cycle time, the disk will take one memory cycle out of $21+1 = \dfrac{1}{21+1} \times 100 \approx 5\%$

(PS: If we consider just one word transfer we add the memory cycle time to the disk transfer time in the denominator but for continuous DMA transfer, this is not required as when data is transferred to main memory, disk can continue reading new data)

4 Comments

see it is mentioned in answer…..percentage of memory cycles stolen for transferring one word (answer is assuming we have only one word to transfer )…

so pipelining concept will come in if we have continuous data to transfer(preparing next word while transferring)

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 Got it brother, Thanks :)

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himanshu2021, without question mark your comment is creating doubt
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59 votes
59 votes
$y \;\mu$s is cycle time / transfer time (for memory)

$x \;\mu$s is data transfer time / preparation time (for disk)

$\%$ of time CPU is idle = $\frac{y}{x+y}$

Maximum bit identity is given, So consider inner most track to get the capacity

It is = $2 \times 3.14 \times 5 \times 1400$ bits $= 3.14 \times 14000$ bits

Rotational latency = $\frac{60}{4200} s = \frac{1}{70}s$

So, $3.14 \times 14000$ bits is read in $\frac{1}{70}s$

Therefore, to read $64$ bits time required = $\frac{{{10}^6} \times 64}{70 \times 3.14 \times 14000}\; \mu s = 20.8 \mu s$

As memory cycle time is $1 \mu s$

$64$ bits are transferred in $1 \mu s$

Therefore $\%$ CPU cycle stolen $= \frac{1}{20.8+1} = 4.58 \%  \approx 5\%$

Correct Answer: $C$
edited by

4 Comments

should we consider the x/y or x/(x+y) as the fraction of CPU block time. We can consider the overlap for the vacation or transfer of and the allocation of the block as the DMA is working in cycle stealing mode as mentioned by @Bikram sir for the following question https://gateoverflow.in/1393/gate2005-70

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why to take cpu busy time % as x/y in cycle stealing mode and not x/(x+y)??
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@VIDYADHAR SHELKE 1 both have same capacity... Inner most has high density ,outer most has low density...

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34 votes
34 votes

Track Capacity = density*parimeter
=1400 bits/cm*2*pi*5cm = 14000*pi bits = 43960 bits/track       $\because pi=3.14$

Track Capacity = 43960 bits/track

Transfer rate = 43960*70 = 30,77,200 bits/sec
 

Data needs to be transferred =8 Bytes or 64 bits,  cycle time= 1 microsec

 Time to transfer 64bits = $\frac{64}{30,77,200}$ = 20.8 microseconds or 21 memory cycles
For each 21 memory cycle, 1 memory cycle will be taken to transfer data. CPU can do its own work for 20 memory cycles and 1 memory cycle it will remain idle.
%of memory cycles stolen = $\frac{1*100}{21}$ = 4.76% or approx. 5%

edited by

4 Comments

i think this line is wrong because cpu will not be idle 

@Swapnil Naik 1) DMA controllers can operate in a cycle stealing mode in which they take over the bus for each byte of data to be transferred and then return control to the CPU

2) The CPU doesn't stay idle at all. It just gives the control of the data Bus to the DMA for 1 memory cycle . DMA transfers the data in this cycle which is consistent with it's transfer rate. Meanwhile the CPU can perform operations which do not involve the memory bus (by the means of cache memory and registers). 

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I think once the 64 bit data is generated in the memory, now cpu has to transfer it. For transferring data bus access will be given to dma, so now dma is going to steal 1 cycle to transfer data. so it is stealing 1 microsecond out of 20.8 microsecond(as it is in cycle stealing mode data transfer is pipelined fashion) hence for 1 microsecond cpu is not doing anything.

Reason - if you see pipeline architecture there are DMA breakpoints, and to complete dma request cpu can leave an instruction at any stage without consideration of it has to complete instruction and then execute dma request. so now cpu is busy for 1 microsecond for transfer and hence it is idle.
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How can 1 memory cycle be used to transfer data to memory if 21 memory cycles are required to transfer the data from the disk to memory. If CPU transfers the control to DMA for only one memory cycle then what happens during the 21 memory cycles when the data is actually being transferred?
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30 votes
30 votes

As the max density is given so we take the inner most diameter as it is denser there(2Rpi). The capacity of each track is pi*D*Density=3.14*10*1400 bits=14000pi bits
Now rotational latency is 60/RPM=60/4200=1/70 s.

So in 1/70 sec the disk can traverse one entire track and can read total 14000pi bits. Now this is done by the cpu. Now the data transfer is done by the DMA controller which will be operated in memory cycle time i.e 1 micro sec and it has 64 bit word length. So in 1 cycle it is able to transfer total of 64 bits. In 1 sec it can transfer 64*10^6 bits.(1sec memory cycle)
In 1 sec the disk can read total of 14000pi*70=3.08*10^6 bits (considering pi=22/7)
So total memory cycle stolen is 3.08*10^6/(64*10^6) %= 5%(approx)

1 comment

@Arjun sir @Kapilp @manojk ...ans should be like this 3.08/(3.08+64) = 0.04591 * 100 = approax= 5 or i'm missing something ??
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