Q31). Consider a pipeline "x" consist of $5$ stages names as $IF$,$ID$,$OF$,$EX$ and $WB$ with the respective stage delays of $2 \text{ns}$ ,$5 \text{ns}$, $6 \text{ns}$ and $1 \text{ns}$ .The alternative pipeline "y" contains the same number of stages but $EX$ stage is divided into $4$ sub stages, $(EX1,EX2,EX3 \ and \ EX4)$ with equal delay i.e. $(8 ns/4)$ and $ID$ stage is divided into $2$ substages $(ID1 \ and \ ID2)$ with equal delays of $(5 ns/2)$. In the pipeline 'x' and 'y' memory reference instructions are not overlapped so the penalty of memory reference instructions in the pipeline'x' is $4 \ \text{cycles}$ and in the pipeline 'y' is $8 \ \text{cycles}$.If the program contains $30 \%$ of the instructions which are memory based instructions, the speedup ratio of 'x' is speedup ratio of 'y' is _______
please elaborate on it ?
