Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF, ID, OF and WB stages takes 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction, 4 clock cycles for MUL instruction and 3 clock cycles for DIV instructions respectively.
How many clock cycles needed to execute the above sequence of instruction, where operand forwarding from PO to PO?