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Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF, ID, OF and WB stages takes 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction, 4 clock cycles for MUL instruction and 3 clock cycles for DIV instructions respectively.

How many clock cycles needed to execute the above sequence of instruction, where operand forwarding from PO to PO?

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I am getting 13 cycles as answer .

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$k+(n-1) = 5+(4-1)=8$ $+3+2(additional \hspace{0.1cm} cycles\hspace{0.1cm} in \hspace{0.1cm}PO \hspace{0.1cm}stage) = 13 \hspace{0.1cm}cycles$

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