GATE Overflow Test Series | Mock GATE | Test 6 | Question: 38

Question

Consider a $5$-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (Memory), and WB (Write Back). All register reads take place in the second phase of a clock cycle and all register writes occur in the first phase and there is no operand forwarding in use. Consider the execution of the following instruction sequence:

• $I_1: R_1 \leftarrow R_2 + R_3$
• $I_2: R_3 \leftarrow R_1 - R_2$
• $I_3: M[R_3] \leftarrow R_1$
• $I_4: R_2 \leftarrow R_3 * R_1$

If the number of RAW (Read after write) hazards is denoted by $A,$ WAR (Write after read) hazards by $B$ and WAW (Write after write) hazards by $C,$ then $2A+3B+C =$ ___________

Answer 1

RAW dependencies:

1. $I_1 \to I_2$
2. $ I_1 \to I_3$
3. $I_1 \to I_4$
4. $ I_2 \to I_3$
5. $ I_2 \to I_4.$

Among these $I_1 \to I_4$ is not causing any stalls in the pipeline and is so not a hazard. The number of RAW hazards is $4.$

$$\begin{array}{|c|c c c c c c c c c c c c|}
\hline
&1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 & 9 & 10 & 11& 12\\
\hline
I_1&\text{F}&\text{D} &\text{E} &\text{M} &\textbf{W} & & & &&&&\\
I_2&&\text{F} &&&\boxed{\text{D}} &\text{E} &\text{M} &\textbf{W} & &&& \\
I_3&& &&&\text{F} &&&\boxed{\text{D}} &\text{E}  &\text{M}  &\text{W} & \\
I_4&& & &&&&& \text{F} &\boxed{\text{D}} &\text{E}  &\text{M} &\text{W} \\
\hline
\end{array}$$
In an inorder pipeline we won't have WAW or WAR hazards. So, $2A + 3B + C = 8.$

Comments

Then I2->I4 also not creating RAW hazards I think

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Why fetching of I3 and I4 is delayed by 2 clocks?

Can't we fetch the I3 in 3rd clock and I4 in 4th clock?

Please clarify it

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@deviantpadam no we cannot 
In pipelining if we fetch the next instruction before the current one is decoded, data of currently fetched instruction is lost and overwritten by the next instruction fetch. Same for other stages too.