Physical memory = 64KB ===> 16 bits required to represent Physical memory
Cache memory = 2KB ===> 11 bits for cache memory
Block size = 64 B = 32 words ===> 6 bits because of system is Byte addressable.
Tag = 16-11 = 5 bits
Cache index = 11-6 = 5 bits
Block offset = 6 bits
P = 0XA248 = 1010 0010 0100 1000 = $10100\; \color{red}{01001}\; 001000$ ( Tag – cache index – Block offset )
Q = 0XC28A = 1100 0010 1000 1010 = $11000\; \color{red}{01010}\; 001010$
R = 0XCA8A = 1100 1010 1000 1010 = $11001\; \color{red}{01010} \;001010$
S=0XA262 = 1010 0010 0110 0010 = $10100\; \color{red}{01001} \;100010$
Given that, Direct mapped cache,
If we observe, P and S are belongs to same Block ( Tag and cache bits are same ). Therefore every access of S should result in a hit due to neither Q nor R competing for the same cache block and once P brought to the cache, it is never evicted.
If we observe Q and R, those are competing for same cache block. So at the end R only present in the cache due to R is accessed at last. ( compaing to Q ) and every access to R evicts Q from the Cache.
Therefore at the end, P,R and S in the Cache.
Options A,B and D are true.