Very good question they wanted to check the implementation details of the whole circuitry and the combinational circuits used.
1. Okay so we have a 16 bit code word, that is made up of Mode bit, S-address and a R-address. Now in the T (say container or say location) we are getting the output of “S” and “R”. Also we have our mode bit supplied. Now we can roughly deduct that it’s something related to a multiplexer. But don’t let just assume things.
2. So our “S” is a 1024 word memory segment meaning there are (2 to the power 10) 10 bits to represent 1024 words. Similarly for “R” 5 bits are used (2 to the power 5).
3. In P there is a circuit that is taking some input out of the S-address and making it a “2 to the power 10” output. One such circuit is a decoder. It can’t be a multiplexer as there is no select line to choose an input line and produce output accordingly. So option A and D are ruled out.
4. Now in Q there is a circuit that is taking some input and converting it into a “2 to the power 5” output. One such circuit is a decoder. As both B and C satisfies this requirement so no option can be ruled out.
5. Now all that remain is “T”, out of the options remaining it can be either a multiplexer or an encoder. Now both of these circuits functionality are identical and the only difference is the select line. A multiplexer needs a select line to generate output or we can say an encoder with an enable line is called a multiplexer. And for this case as M is serving as an enable or select line we can rule out the possibility of T space to have an encoder.
Therefore option C is correct.
Now once laying out the circuits at their positions we can check the whole circuitry to see if it’s valid or not.
We said P is 10:2 to the power 10 decoder therefore S-address = 10 bits.
We said Q is 5:2 to the power 5 decoder therefore R-address = 5 bits
We assumed mode bit to be 1.
So adding them up gives 10 + 5 + 1 = 16 bit, that was the original codeword given in the question.