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Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ is a write through cache. Which of the following statements is/are $\text{FALSE}?$

  1. Each cache block in $\text{WB}$ and $\text{WT}$ has a dirty bit.
  2. Every write hit in $\text{WB}$ leads to a data transfer from cache to main memory.
  3. Eviction of a block from $\text{WT}$ will not lead to data transfer from cache to main memory.
  4. A read miss in $\text{WB}$ will never lead to eviction of a dirty block from $\text{WB}.$
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Option: A, B, D

WB Cache: Updates to the cache block don’t result in Updates to the Main Memory immediately. Burst Writes are preferred for higher throughput and those needing higher write performance.

WT Cache: Updates to the Cache block are reflected on Main Memory before carrying out other processes. Consistency is preferred.

  1. A WB must necessarily have a dirty bit to avoid redundant writes to Main Memory. Whereas a WT cache needn’t as the change is reflected after a write. False
  2. A WB cache’s primary use is to increase throughput or useful work. Multiple writes to the same cache block will not be reflected immediately, avoiding unnecessary data transfer time. False
  3. WT cache’s main goal is to prefer consistency overwrite performance, and a cache block is made to reflect the current main memory. True
  4. LRU doesn’t have specific replacement strategies for dirty and regular blocks. Hence a read miss might evict a dirty block. False
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