made easy test series

Question

Consider a pipelined processor with the stages IF, ID, EX and WB. IF, ID and WB. Stages takes one clock cycle each to complete the operation and EX stage depends on the instruction. ADD and SUB need 1 clock cycle. MUL and DIV need 3 clock cycles each. What is the number of cycles needed to execute the following sequence of instructions?

                                               

(Assume there is no hardware to reduce stalls)

• 10
• 11
• 12
• 13

Answer 1

ya answer should be 11