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Accumulator CPU is example of One Address Instruction:

In Acc. CPU first alu operand is always required in the accumulator but second alu operand can be in the register or memory because of the the availability of the one address along with the opcode.

Load and Store is One address Instruction

X= (M + N x O)/(P x Q)

I1: Load P : ACC<--M[P] //Load the P value from memory to ACCUMULATOR

I2: Mul Q: ACC<--ACC*M[Q] //Second alu operand is in memory and destination is Register

I3: Store T: M[T]<--ACC //Store the Value in memory

I4: Load N : ACC<--M[N]

I5: Mul O : ACC<--ACC*M[O]

I6: Add M: ACC<--ACC+M[M]

I7: Div T: ACC<--ACC/M[T]

I8: Store X: M[X]<--ACC //Finally store in value in memory

TOTAL 8 1 ADDRESS INSTRUCTION REQUIRED.

0

Thanks a lot.

So basically whenever one address instruction is asked, we have to put data in ACC and modify it? Also, in inst I5, its M[O] instead of M[N] i guess.

So basically whenever one address instruction is asked, we have to put data in ACC and modify it? Also, in inst I5, its M[O] instead of M[N] i guess.

+5 votes

1. LDA P ; AC<----M[P]

2. MUL Q ; AC<----AC*M[Q]

3. STA Y ; M[Y]<----AC

4. LDA N ; AC<----M[N]

5. MUL O ; AC<----AC*M[O]

6. ADD M ; AC<----AC+M[M]

7. DIV Y ; AC<----AC/M[Y]

8. STA X ; M[X]<----AC

Hence it will require minimum 8 instructions to evaluate....

2. MUL Q ; AC<----AC*M[Q]

3. STA Y ; M[Y]<----AC

4. LDA N ; AC<----M[N]

5. MUL O ; AC<----AC*M[O]

6. ADD M ; AC<----AC+M[M]

7. DIV Y ; AC<----AC/M[Y]

8. STA X ; M[X]<----AC

Hence it will require minimum 8 instructions to evaluate....

+2 votes

Is this answer Correct? pls correct if any mistakes

**Zero Address **

- PUSH P
- PUSH Q
- MUL
- PUSH O
- PUSH N
- MUL
- PUSH M
- ADD
- DIV
- POP X

**One Address**

- LOAD P
- MUL Q
- STORE T
- LOAD O
- MUL N
- ADD M
- DIV T
- STORE X

**Two Address **

- MOV R1,N
- MUL R1,0
- ADD R1 ,M
- MOV R2,Q
- MUL R2,P
- DIV R1,R2
- MOC X,R1

**Three Address**

- ADD R1,P,Q
- MUL R2,N,O
- ADD R2,R2,M
- DIV X,R2,R1

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