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+26 votes

Which of the following input sequences will always generate a $1$ at the output $z$ at the end of the third cycle?

0

Kindly make the question more clear ! Third cycle here means that after giving the last input. for example in the first option after we give A,B and C : 1 1 1 , the the output should be 1 at z. Is this what is meant by the third cycle ??

+6

Its a GATE question :) If you see the circuit, z depends on the previous output. And thats why 3 sets of inputs are given.

+4

After the second cycle **the value of Q should be 0**, which is not happening in any of the options, hence something is wrong.

Anyway, i couldn't understand one thing, will the same clock pulse be applied together to both the flipflops?

0

yes, manu I think both of them should be applied together this type of representation occur many times in questions but I think for a circuit there exist only a single clock pulse, this representation might be used to make diagram look cleaner.

+35 votes

$${\begin{array}{|c|c|c|c|c|c|c|l|}\hline\\

\textbf{}& \textbf{A}& \textbf{B}&\bf{C}& \bf{Q_1}& \bf{Q_2} & \textbf{Z} & \textbf{Comment}\\\hline

\text{After } 1^{st} \text{Cycle} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} \\\hline \text{After } 2^{nd} \text{Cycle}&0&0&\text{X}&0&\text{X} & \text{X}& \text{$Q_1$ is 0 making A and B 0}\\ \hline \text{After } 3^{rd} \text{Cycle}&\text{X} &\text{X} &1&1&1&1& \text{$Z$ is $1$ making $Q1$ and $Q2$ $1$,}\\&&&&&&&\text{Either $A$ or $B$ is $1$.} \\&&&&&&&\text{$Q1'$ of previous cycle is $1$.} \\ \hline

\end{array}}$$

The filling is done in reverse order. Here, none of the options match. So, something wrong somewhere.

\textbf{}& \textbf{A}& \textbf{B}&\bf{C}& \bf{Q_1}& \bf{Q_2} & \textbf{Z} & \textbf{Comment}\\\hline

\text{After } 1^{st} \text{Cycle} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} \\\hline \text{After } 2^{nd} \text{Cycle}&0&0&\text{X}&0&\text{X} & \text{X}& \text{$Q_1$ is 0 making A and B 0}\\ \hline \text{After } 3^{rd} \text{Cycle}&\text{X} &\text{X} &1&1&1&1& \text{$Z$ is $1$ making $Q1$ and $Q2$ $1$,}\\&&&&&&&\text{Either $A$ or $B$ is $1$.} \\&&&&&&&\text{$Q1'$ of previous cycle is $1$.} \\ \hline

\end{array}}$$

The filling is done in reverse order. Here, none of the options match. So, something wrong somewhere.

0

@Arjun: I am getting option (D) as answer.

You must take care that the value of **~Q** **that is ANDed with C** **is actually the initial value of of ~Q before giving any input or triggering the ****CLOCK pulse.**

**If we assume that Q is zero initially, we get ~Q=1 and this is ANDed with first C bit to produce the Z for that particular cycle.**

**Please verify this.**

+7

characteristic equation of D FF is Qn+1=D

1st D FF output is (A+B)

2nd D FF output is (A+B)'C

and final result Z=(A+B).((A+B)'C)=(A+B)(A'B'C)=0

all options are wrong

1st D FF output is (A+B)

2nd D FF output is (A+B)'C

and final result Z=(A+B).((A+B)'C)=(A+B)(A'B'C)=0

all options are wrong

+1

Sir i think they asked for which set the output will be one . for c it will be always one . how you answered this. I can't understand it.

0

if i assume Q=0 intially , so Q'=1 which is input of second one D flip flop then i got B option as answer

+7

**If we write the equation then we get Z=( A+B ). ( C. (A+B)' )**

**As . (And is associative)**

**so we can write it as Z= ((A+B). (A+B)'). C**

** Z=0.C**

** Z=0 **

**Hence it is giving us 0 always it means all options must be wrong!!!!**

+1

@Arjun sir, what to do when these type of questions come in gate exam, such that no option matches? Were marks given to all in this question in 2005?

+1

Your approach is wrong .You cant make A=B=Q1=0 in same cycle. Input at D1 will appear as output in Q1 in the next cycle . Consider same for second flip flop , you will get A as the answer.

0

Sir, even I am getting 0 for z in all the options. Why are you saying to fill the table in reverse order.

I solved it using the given order only by forming equation of z ( z = (a+b).c.(a_{p'}.b_{p'}))

Where _{p }denotes values of a and b from previous cycle.

Am I doing wrong somewhere?

0

@Sid1221.. This assumption is wrong because if no input is given to the first input terminal of the first AND gate , that input will be considered as zero, so it is of no use to assume Q1=0 here. Correct me if I am wrong.

0

@Arjun sir, in first clock cyle , since there is no input in first input terminal of AND gate, so what should we assume, ....zero or it has to be assumed according to ~Q initially i.e. if I assume Q to be 0 initially, then ~Q will be 1. So which value should be taken as input to first terminal of first AND gate??

please tell.

please tell.

+4 votes

+2 votes

I am getting Option(a) as the correct answer. If wrong please rectify it.

I have taken the initial state as 0.

+2 votes

Answer is C

Explanation:

Here given in question first O/P Z is always 1 at the end of third cycle.

(I have consider first f/f Q as Q0 and second below f/f as Q1)

So Z=1

now for Z=1

Iff Q0 and Q1 are 1.

for Q0=1:

Either A or B should 1 or Both

i.e.

A B

0 1

1 0

1 1

Now for Q1=1:

Q0'.C=1 only when Q0=0 and C=1

Now combine the Input sequences(for both Q0=1 and Q1=1):

A B C

0 1 1

1 0 1

1 1 1

So, C is the Answer here.

Explanation:

Here given in question first O/P Z is always 1 at the end of third cycle.

(I have consider first f/f Q as Q0 and second below f/f as Q1)

So Z=1

now for Z=1

Iff Q0 and Q1 are 1.

for Q0=1:

Either A or B should 1 or Both

i.e.

A B

0 1

1 0

1 1

Now for Q1=1:

Q0'.C=1 only when Q0=0 and C=1

Now combine the Input sequences(for both Q0=1 and Q1=1):

A B C

0 1 1

1 0 1

1 1 1

So, C is the Answer here.

+1 vote

A | B | C | $D_{top}$ | $D_{bottom}$ | $Q_{top}$ | $Q_{bottom}$ | Z | Remark/Comment |

X | X | X | X | X | 1 | 1 | 1 | Final Value |

1 | 0 | 1 | 1 | 1 | 0 | X | X | Required Value before $3^{rd}$ clock |

0 | 0 | X | 0 | X | X | X | X | Required Value before $2^{nd}$ clock |

X | X | X | X | X | X | X | X | Required Value before $1^{st}$ clock |

In the $2^{nd}$ row (from top). Following values are also possible.

0 | 1 | 1 | 1 | 1 | 0 | X | X | Required Value before $3^{rd}$ clock |

1 | 1 | 1 | 1 | 1 | 0 | X | X | Required Value before $3^{rd}$ clock |

So non of the options are matching. I hope this helps.

ping @Krish__, @rahul sharma 5, @Red_devil, @Shivam Chauhan, @Tuhin Dutta, @Anu007, @Ashwin Kulkarni @reena_kandari and @srestha ji

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