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A hardwired CPU uses $10$ control signals $S_1$ to $S_{10}$, in various time steps $T_1$ to $T_5$, to implement $4$ instructions $I_1$ to $I_4$ as shown below:

$$\begin{array}{|c|c|c|c|c|c|}\hline&\bf{T_1}&\bf{T_2}&\bf{T_3}&\bf{T_4}&\bf{T_5}\\\hline\bf{I_1}&S_1,S_3,S_5&S_2,S_4,S_6&S_1,S_7&S_{10}&S_3,S_8\\\hline\bf{I_2}&S_1,S_3,S_5&S_8,S_9,S_{10}&S_5,S_6S_7&S_{6}&S_{10}\\\hline\bf{I_3}&S_1,S_3,S_5&S_7,S_8,S_{10}&S_2,S_6,S_{9}&S_{10}&S_1,S_3\\\hline\bf{I_4}&S_1,S_3,S_5&S_2,S_6,S_7&S_5,S_{10}&S_{6},S_9&S_{10}\\\hline\end{array}$$

Which of the following pairs of expressions represent the circuit for generating control signals $S_5$ and $S_{10}$ respectively?

$((I_j + I_k)T_n$ indicates that the control signal should be generated in time step $T_n$ if the instruction being executed is $I_j$ or $l_k)$

  1. $S_5 = T_1 + I_2 \cdot T_3$ and

    $S_{10} = (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5$

  2. $S_5 = T_1 + (I_2 + I_4) \cdot T_3$ and

    $S_{10} = (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5$

  3. $S_5 = T_1 + (I_2 + I_4) \cdot T_3$ and

    $S_{10} = (I_2 + I_3 + I_4) \cdot T_2 + (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5$

  4. $S_5 = T_1 + (I_2 + I_4) \cdot T_3$ and

    $S_{10} = (I_2 + I_3) \cdot T_2 + I_4 \cdot T_3 + (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5$

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$D$. is the correct option for this question.
If we look at the table, we need to find those time-stamps and instructions which are using these control signals.

For example, $S_5 = T_1$ has used control signal $S_5$ for all the instructions, or we can say irrespective of the instructions. Also, $S_5$ is used by instructions $I_2$ and $I_4$ for the time stamp $T_3$ so that comes to:
$$S_5 = T_1 + I_2 \cdot T_3 + I_4 \cdot T_3 = T_1 + (I_2+I_4) \cdot T_3$$

In the same way, we'll calculate for $S_{10}$.
It's an example of Hardwired CU Programming used in RISC processors. It gives accurate result, but isn't good for debugging since minor change will cause to restructure the control unit.
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