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Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache.

Assume that miss penalty from the L2 cache memory $50$ cycles. The hit time of L2 cache is $10$ cycles. The hit time of the L1 cache is $5$ cycles.

If there are $1.25$ memory references per instruction, then the average stall cycles per instruction is ________.


answer given is $4$
in CO and Architecture by Boss (16.2k points)
edited by | 195 views

2 Answers

+4 votes

no of instruction 200 = (250/1.25).

now stall/instruction is = miss in L1 / inst. * hit in L2  + miss in L2 / inst. * miss penalty in L2

                                    = (30/200)*10 +(10/200)*50 =4

by Loyal (6.4k points)
+3 votes
first 1.25 memory references per instruction means total no. of instruction is 250/1.25 =200 instructions
Now total cycle required to execute all instruction
220*L1{Hit time} + 20*L2{Hit time} + 10*l2{penalty time}
220*5+20*10+10*50=1800 cycles

each instruction take 1800/200 =9 cycles
Now consider there is no misses and latency So all instruction execute in 200*5=1000 or say each instruction execute in 5 cycleSo stall is 9-5=4 cycle
by Active (1.1k points)
reshown by
can you please explain how you calculated total cycle time again?
here total 250 memory reference and 30 misses in L1 means 220 hit in L1 now now if 30miss in L1 now we look in L2 and in L2 only 20 hit and 10miss 10miss in L2 means penalty is 50cycle for this 10miss

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