Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache.
Assume that miss penalty from the L2 cache memory $50$ cycles. The hit time of L2 cache is $10$ cycles. The hit time of the L1 cache is $5$ cycles.
If there are $1.25$ memory references per instruction, then the average stall cycles per instruction is ________.
answer given is $4$