in CO and Architecture
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in CO and Architecture
107 views

4 Comments

@DebSujit

i don’t know how they are getting F2 value for the 3rd Instruction from 2nd instruction before the WB stage of 2nd instruction

Actually they are splitting cycle in two phases in first half of the cycle they are writing in the register and second half they are reading from the register

https://gateoverflow.in/275371/pielining-doubt

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Is split phase mentioned in the question? I thought we could only use that if it is mentioned in the question.
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It's just as optimization that register writes are made in the first half of the clock cycle and register reads are made in the second half of the clock cycle.
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