0 votes 0 votes CO and Architecture pipelining co-and-architecture + – lalitver10 asked Sep 10, 2022 lalitver10 359 views answer comment Share Follow See all 8 Comments See all 8 8 Comments reply lalitver10 commented Sep 10, 2022 reply Follow Share Hi All, Is it possible SUBD instruction in this pipeline will completed before the MULTD instruction due to MULTD instruction required more no of cylce in EX stage ?? 0 votes 0 votes DebRC commented Sep 11, 2022 reply Follow Share @lalitver10 It is possible.Is this the answer? 3 votes 3 votes lalitver10 commented Sep 11, 2022 reply Follow Share @DebSujit Yes total no of Cycle required are 19. Thanks. 0 votes 0 votes DebRC commented Sep 11, 2022 reply Follow Share Most pipeline structures fetches register operand at Instruction Decode stage as far as i knew. Without operand forwarding, i don’t know how they are getting F2 value for the 3rd Instruction from 2nd instruction before the WB stage of 2nd instruction. Although, there could be multiple structures for a given pipeline. All, would lead to 19 cycles if packed properly. 0 votes 0 votes DebRC commented Sep 11, 2022 reply Follow Share At the same time the register file is read, instruction issue logic in this stage determines if the pipeline is ready to execute the instruction in this stage.Written in https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Instruction_decode 0 votes 0 votes lalitver10 commented Sep 11, 2022 reply Follow Share @DebSujit i don’t know how they are getting F2 value for the 3rd Instruction from 2nd instruction before the WB stage of 2nd instruction Actually they are splitting cycle in two phases in first half of the cycle they are writing in the register and second half they are reading from the register https://gateoverflow.in/275371/pielining-doubt 1 votes 1 votes DebRC commented Sep 11, 2022 reply Follow Share Is split phase mentioned in the question? I thought we could only use that if it is mentioned in the question. 0 votes 0 votes lalitver10 commented Sep 11, 2022 reply Follow Share It's just as optimization that register writes are made in the first half of the clock cycle and register reads are made in the second half of the clock cycle. 1 votes 1 votes Please log in or register to add a comment.
0 votes 0 votes In RISC 5 Stage pipeline Register read is done at 2nd stage. i.e Instruction decode. Also WB stage has half cycle for write and other half for register read. So, considering this we will get 19 clock cycles. supreetshukla answered Jan 25, 2023 supreetshukla comment Share Follow See all 0 reply Please log in or register to add a comment.