in CO and Architecture
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in CO and Architecture
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Hi All,

  Is it possible SUBD instruction in this pipeline will completed before the MULTD instruction due to MULTD instruction required more no of cylce in EX stage ??
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@lalitver10 It is possible.

Is this the answer?

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@DebSujit 

Yes total no of Cycle required are 19.

Thanks.

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Most pipeline structures fetches register operand at Instruction Decode stage as far as i knew. Without operand forwarding, i don’t know how they are getting F2 value for the 3rd Instruction from 2nd instruction before the WB stage of 2nd instruction.

Although, there could be multiple structures for a given pipeline. All, would lead to 19 cycles if packed properly.

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At the same time the register file is read, instruction issue logic in this stage determines if the pipeline is ready to execute the instruction in this stage.

Written in https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Instruction_decode

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@DebSujit

i don’t know how they are getting F2 value for the 3rd Instruction from 2nd instruction before the WB stage of 2nd instruction

Actually they are splitting cycle in two phases in first half of the cycle they are writing in the register and second half they are reading from the register

https://gateoverflow.in/275371/pielining-doubt

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Is split phase mentioned in the question? I thought we could only use that if it is mentioned in the question.
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It's just as optimization that register writes are made in the first half of the clock cycle and register reads are made in the second half of the clock cycle.
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1 Answer

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In RISC 5 Stage pipeline Register read is done at 2nd stage. i.e Instruction decode.

Also WB stage has half cycle for write and other half for register read.

So, considering this we will get 19 clock cycles. 

ago

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