0 votes 0 votes How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable. CO and Architecture co-and-architecture memory-interfacing + – shreyo asked Sep 12, 2022 • retagged Sep 12, 2022 by makhdoom ghaya shreyo 506 views answer comment Share Follow See all 9 Comments See all 9 9 Comments reply RamaSivaSubrahmanyam commented Sep 12, 2022 reply Follow Share It needs 3*8 decoder .. 0 votes 0 votes shreyo commented Sep 12, 2022 reply Follow Share Can u provide me a full solution to this... It's confusing 0 votes 0 votes Vishnu__ commented Sep 16, 2022 reply Follow Share 64 chips and 20x2^20 size-decoder is needed. 0 votes 0 votes RamaSivaSubrahmanyam commented Sep 16, 2022 reply Follow Share @Vishnu__ No, that's wrong .. 0 votes 0 votes Vishnu__ commented Sep 16, 2022 reply Follow Share @RamaSivaSubrahmanyam then wt is the crct soln? 0 votes 0 votes RamaSivaSubrahmanyam commented Sep 16, 2022 reply Follow Share ,here each chip addresses 2^17 locations ... To adressses 2^20 locations (1MB) ,we need another 2^3 chips ,so 8 chips can be address 8*2^17 addresses, so total 2^20 addresses… … We need actually 64 chips .. For address part we only required 8 chips which can be selected by 3*8 decoder 1 votes 1 votes Vishnu__ commented Sep 16, 2022 reply Follow Share Okay this is abt chip-select decoder, right? 0 votes 0 votes RamaSivaSubrahmanyam commented Sep 16, 2022 reply Follow Share Indeed.. 0 votes 0 votes RamaSivaSubrahmanyam commented Sep 16, 2022 reply Follow Share @Vishnu__.. look at the answer below,it will tell how the actual things happen in the architecture..[demo] 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes it's just a demo... RamaSivaSubrahmanyam answered Sep 12, 2022 RamaSivaSubrahmanyam comment Share Follow See all 0 reply Please log in or register to add a comment.
