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The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline has 5 stages IF, ID EX, MA and WB and their is no data and control hazard. The number of clock cycles required for execution of sequence of instruction are ________.

my ans is 354 where iam wrong.

approch  totel 200 in which (100 add having 1 cc)  +(25*5-1) +(75*(3-1))=354
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There are 200 instructions
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@afroze yes  from out of 200 we take 100 for add 25 for div and 75 for mul so 100+25+75=200

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@jugnu1337 you considered only stall cycles

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Lets consider that every instruction takes one cycle for execution .

As there are 200 instructions and 5 stages so (k+n-1) clock cycles for the execution = 5+200-1 = 204 CC.

Now consider the fact that it requires 5 clock cycles for division and 3 clock cycles for multiplication . there are extra 4 clock cycles due to division and 2 clock cycles due to multiplication .

Hence there are 25*4 = 100 stall cycles due to Division and 75*2 = 150 stall cycles due to mutiplication.

Total Cycles = 204+100+150 = 454 .
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There are total 200 Instruction

Total No Of cycle Required : (5+(200-1))+75*2+25*4 => 454

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