Consider the following sequence of micro-operations (μO) on a system used for instruction fetch:
Where MAR is memory address register, PC is program counter, MBR is memory buffer register and IR is instruction register. And Mem[MAR] means reading data from memory location provided in MAR. Assume each μO takes 1 cycle. Which of the following μO’s can execute parallely without conflict.
If we consider split cycle scenario we can divide the cycle into two halves such that in the first half PC is written into MAR and in the second half PC is incremented and moreover in the question it is saying “can execute parallely without conflict”. So that is why I guess b is also a viable option as this scenario is possible. That is why a,b,c are possible options.
@Sunnidhya Roy i agree to your argument, but we should not assume split phase if not mentioned
@Shubhodeep In the question it is mentioned “can execute paralley” that is why I am saying b can be a viable option.