CO and Arcitecture | RISC | Instruction pipelining

Question

MSQ

Which among the following statements is/are TRUE  for a pipelined RISC computer.

1. PC is usually incremented during Instruction Cycle (IF,ID)
2. PC may be incremented during Execution Cycle (EX,MA,WB)
3. Filling the Accumulator register and Temporary register with General purpose register values maybe done during the Execution Cycle (EX,MA,WB)
4. Filling the Accumulator register and Temporary register with General purpose register values maybe done during the Instruction Cycle (IF,ID)
5. All non-register memory fetching operations are done in Load instructions only.

Comments

@Souvik33 1,4 and 5?

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@Sunnidhya Roy 2 can be correct in case of Indirect addressing or Relative addressing calculations.

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I was also thinking that Ideally speaking during Branching Pipeline's last stage can perform PC manipulations if pipeline is flushed and instructions are newly loaded, sorry for writing in my native Language.

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@DebSujit got a thread regarding this.

https://cs.stackexchange.com/questions/68872/why-does-the-program-counter-increment-before-an-instruction-is-completed/69137#69137

But Wikipedia mentions that it is usually done in parallel to or after IF stage.

https://www.google.com/search?q=pc+value+can+be+incremented+in+which+stage+if+pipeline&oq=pc+value+can+be+incremented+in+which+stage+if+pipeline&aqs=chrome..69i57.9344j0j4&client=ms-android-oppo-rvo3&sourceid=chrome-mobile&ie=UTF-8#scso=_GgCcY_XEL4qG4-EP6fiEsA0_25:144

 

These are implementation specific questions, there might not be any absolute answer.

 

Answer 1

I think correct answer is option $(1),(3),(5)$ .

In RISC computer the fetch cycle looks like,

$1)MAR\leftarrow PC$

$2)MBR\leftarrow MEMORY[MAR]$

$3)IR\leftarrow MEMORY[MAR];PC\leftarrow PC+1$

So, PC is incremented in fetch stage only in RISC architecture.

If we think about option (2) it will fail in case of pipelining as if we increment PC in execute state then we have to keep ideal till execute stage comes to fetch new instruction which include more stall cycles and reduce efficiency of the pipeline . So option (2) is false .

Option (3) is not necessarily correct as counter example 

$LDA $ $x$  [$x$ is a memory address]

Now in fetch cycle we already describe above .

Decode stage decode it from instruction register [$IR$] found it as a load instruction .

Instruction stage :-

$1)MAR\leftarrow X$

$2)MBR\leftarrow MEMORY[X]$

$3)AC\leftarrow MBR$

 So, filling of accumulator done in execute stage .

option (5) is correct as in RISC all memory fetching operation generally done using load instructions .

https://www.robots.ox.ac.uk/~dwm/Courses/2CO_2014/2CO-N2.pdf

Answer 2

My views are:

1. When we are using System Bus to execute M[MAR] → MBR, local bus is free, even if we do not have a dedicated ALU for PC incrementation, we can complete this task in this cycle, so possible in Instruction cycle.
2. Even tough there is absolutely no need to increment PC in execution cycle, we can still do it in some cases, maybe when we go for a write back using the system bus, cpu is free, we can do it here, but I’m not sure about this, but we generally don’t do that.
3. This posibly never happens
4. This is the normal situation
5. This is TRUE, memory fetching is only fetching, not writing back, so as RISC does all it’s work with register values, it needs extra LOADS only to fetch data for other instructions.

Ans: All options execpt 3

 

Comments

Question is about RISC architecture not any hypothetical architecture .

Answer 3

The following statements are true for a pipelined RISC computer:

• PC may be incremented during Execution Cycle (EX,MA,WB)
• Filling the Accumulator register and Temporary register with General purpose register values are done during the Execution Cycle (EX,MA,WB)

The following statement is false:

• PC is incremented during Instruction Cycle (IF,ID)

The statement "All non-register memory fetching operations are done in Load instructions only" is not necessarily true for a pipelined RISC computer. Load instructions are used to fetch data from memory and store it in a register, but other instructions such as stores may also access memory to store data.